10th Class Physics Notes 2026 — Chapter 18 – Federal Board

Class 10 Physics – Chapter 18: Electronics

Board: Federal Board (FBISE)

Multiple Choice Questions

1. The approximate potential barriers for germanium and silicon transistors are, respectively:

A. \(0.3\,\text{V}\) and \(0.7\,\text{V}\)
B. \(0.7\,\text{V}\) and \(0.3\,\text{V}\)
C. \(0.7\,\text{V}\) and \(0.5\,\text{V}\)
D. \(0.5\,\text{V}\) and \(0.7\,\text{V}\)

Correct Answer: A. \(0.3\,\text{V}\) and \(0.7\,\text{V}\)

2. The current ratio beta (\(\beta\)) is:

A. \(\dfrac{I_C}{I_E}\)
B. \(\dfrac{I_B}{I_C}\)
C. \(\dfrac{I_C}{I_B}\)
D. \(\dfrac{I_E}{I_B}\)

Correct Answer: C. \(\dfrac{I_C}{I_B}\)

3. Which of the following relations is correct for a transistor?

A. \(I_E=I_B+I_C\)
B. \(I_B=I_E+I_C\)
C. \(I_C=I_E+I_B\)
D. \(I_E=I_C-I_B\)

Correct Answer: A. \(I_E=I_B+I_C\)

4. The heavily doped region of a transistor is:

A. Emitter
B. Collector
C. Base
D. All of these

Correct Answer: A. Emitter

5. A transistor has _______ PN junctions.

A. 1
B. 2
C. 3
D. 4

Correct Answer: B. 2

6. If \(I_E=1\,\text{mA}\) and \(I_C=0.25\,\text{mA}\), then the value of \(I_B\) will be:

A. \(0.75\,\text{mA}\)
B. \(0.95\,\text{mA}\)
C. \(0.65\,\text{mA}\)
D. \(0.85\,\text{mA}\)

Correct Answer: A. \(0.75\,\text{mA}\)

Calculation:

\[ I_B=I_E-I_C \]

\[ I_B=1-0.25=0.75\,\text{mA} \]

7. If the gain \(\beta\) of an NPN transistor is 200 and its collector current is \(4\,\text{mA}\), the value of base current will be:

A. \(20\,\mu\text{A}\)
B. \(25\,\mu\text{A}\)
C. \(30\,\mu\text{A}\)
D. \(35\,\mu\text{A}\)

Correct Answer: A. \(20\,\mu\text{A}\)

Calculation:

\[ I_B=\frac{I_C}{\beta} \]

\[ I_B=\frac{4\times10^{-3}}{200} =2\times10^{-5}\,\text{A} \]

\[ I_B=20\,\mu\text{A} \]

8. The majority charge carriers in the emitter of an NPN transistor are:

A. Pentavalent atoms
B. Electrons
C. Trivalent atoms
D. Holes

Correct Answer: B. Electrons

9. The output of a NAND gate is ‘0’ when:

A. A is ‘1’ and B is ‘0’
B. A is ‘0’ and B is ‘1’
C. Both A and B are ‘0’
D. Both A and B are ‘1’

Correct Answer: D. Both A and B are ‘1’

10. If \(X=A+B\), then \(X\) is 0 when:

A. Both A and B are ‘0’
B. A or B is ‘0’
C. A is ‘0’ and B is ‘1’
D. A is ‘1’ and B is ‘0’

Correct Answer: A. Both A and B are ‘0’

11. The output of a NOR gate is ‘1’ when:

A. Both of its inputs are ‘0’
B. Both of its inputs are ‘1’
C. Any of its inputs is ‘0’
D. Any of its inputs is ‘1’

Correct Answer: A. Both of its inputs are ‘0’

12. The logical operation performed by the given gate is:

A. AND
B. NOR
C. NAND
D. OR

Note: The gate diagram is not included in the supplied material. The source does not provide a separate answer for this question, so the correct option cannot be verified.

Constructed Response Questions

Q1. Follow the directions to respond to the following questions.

Consider the given logic circuit.

(a) Identify the logic gates in the circuit.

Name of Gate 1: AND Gate
Name of Gate 2: NOT Gate

(b) Draw a single logic gate that can replace the given logic circuit.

The combination of an AND gate followed by a NOT gate performs the NAND operation.

Single Gate Name: NAND Gate

Symbol Diagram:

  A ───┬──────┐
       │ NAND ├───○─── X = A · B
  B ───┴──────┘

A standard NAND gate symbol has inputs A and B, with an inversion bubble at the output X.

Q2. Write the expression for the following combination of logic gates. Here A and B are inputs and X is the output. Also complete its truth table.

Boolean Expression:

The upper gate is a NAND gate, giving the output \(\overline{A\cdot B}\).
The lower gate is an OR gate, giving the output \(A+B\).
Both outputs feed into the final AND gate, giving:

\[ X=\overline{A\cdot B}\cdot(A+B) \]

This expression simplifies logically to an XOR gate operation:

\[ X=A\oplus B \]

Completed Truth Table:

A	B	\(X=\overline{A\cdot B}\cdot(A+B)\)
0	0	0
1	0	1
0	1	1
1	1	0

Note: The original source omitted the inversion bar over \(A\cdot B\) in its written NAND expression. The corrected expression above matches the supplied truth table and XOR result.

Short Response Questions

1. How do N-type materials and forward biasing affect semiconductor devices?

N-type materials provide free electrons as majority charge carriers to greatly increase electrical conductivity. Forward biasing reduces the potential barrier across the junction, allowing current to flow easily through the semiconductor device.

2. Why are pentavalent impurities called donors and trivalent impurities acceptors?

Pentavalent impurities donate extra free conduction electrons to the semiconductor crystal structure, while trivalent impurities accept electrons from neighbouring atoms to create mobile positive holes.

3. How do relays improve electrical systems? Give examples.

Relays allow low-power control circuits to safely switch high-voltage electrical circuits without direct physical contact. Examples include automotive starter switches and automated home heating or cooling systems.

4. How do the three terminals of a transistor work together to amplify signals?

A tiny input signal current at the base terminal modulates the primary flow of majority carriers from the emitter. This produces a proportionally larger output current flowing through the collector terminal.

5. Why is one transistor region highly doped and another the smallest in size?

The emitter is heavily doped to inject a large quantity of majority charge carriers into the transistor. The base is made ultra-thin so carriers cross into the collector with minimal recombination.

6. What does the arrow in a transistor symbol represent, and why is it important?

The arrow located on the emitter terminal indicates the direction of conventional current flow during forward bias. It is crucial for identifying whether the device is an NPN or PNP transistor.

7. Explain the normal biasing of an NPN transistor. What happens if it is reversed?

Normal biasing requires a forward-biased base-emitter junction and a reverse-biased collector-base junction for amplification. Reversing these biases cuts off current flow, preventing normal transistor operation.

8. How does biasing (forward or reverse) change the depletion region in a diode?

Forward biasing drives charge carriers towards the junction to narrow the depletion region and enable conduction. Reverse biasing pulls carriers away, widening the depletion region to block current.

9. Why does an N-type or P-type material have zero net charge?

Doping adds neutral impurity atoms containing equal numbers of protons and electrons into the host crystal matrix. Consequently, the overall electrical charge of both N-type and P-type materials remains strictly neutral.

10. Why are NAND and NOR gates called universal gates?

NAND and NOR gates are defined as universal logic gates because any basic logic operation (AND, OR, NOT) can be constructed exclusively using combinations of only NAND gates or only NOR gates.

11. For a NOR gate, how do you determine the output for different inputs?

A NOR gate produces an output of logic ‘1’ only when all of its input terminals are at logic ‘0’. If any single input is set to logic ‘1’, the output immediately switches to logic ‘0’.

12. What makes digital systems better than analogue systems?

Digital systems offer superior noise immunity, high data processing accuracy, ease of programmable storage, and reliable signal transmission compared to continuous analogue systems.

Long Response Questions

1. What is an extrinsic semiconductor? How do impurities affect its conductivity?

Extrinsic Semiconductor

An extrinsic semiconductor is a pure intrinsic semiconductor, such as silicon or germanium, that has been deliberately doped with a trace amount of a specific impurity element to alter and enhance its electrical properties.

Pure semiconductors have very low electrical conductivity at room temperature due to a limited number of free charge carriers.

Effect of Impurities on Conductivity

The process of adding impurity atoms is called doping. Doping drastically increases electrical conductivity by creating an abundance of mobile charge carriers (electrons or holes).

1. N-Type Doping (Pentavalent Impurities)

Impurities such as phosphorus (P), arsenic (As), or antimony (Sb) have 5 valence electrons.
Four valence electrons form covalent bonds with adjacent silicon atoms, while the fifth electron remains loosely bound and easily becomes a free conduction electron.
Because they donate free electrons, pentavalent atoms are called donor impurities. The majority carriers are electrons.

2. P-Type Doping (Trivalent Impurities)

Impurities such as boron (B), gallium (Ga), or indium (In) have 3 valence electrons.
These three electrons form covalent bonds with surrounding silicon atoms, leaving one bond incomplete, which creates a vacancy known as a hole.
Because they readily accept electrons from adjacent bonds, trivalent atoms are called acceptor impurities. The majority carriers are holes.

2. Describe how a PN junction forms and explain the effects of forward and reverse biasing on it.

Formation of a PN Junction

When a P-type semiconductor material is joined seamlessly to an N-type semiconductor material, a PN junction is formed.

Diffusion: Free electrons from the N-side diffuse across the boundary into the P-side, while holes from the P-side diffuse into the N-side.
Depletion Region: Near the junction, diffusing electrons recombine with holes. This leaves behind uncompensated positive donor ions on the N-side and negative acceptor ions on the P-side, forming a region depleted of free charge carriers called the depletion layer.
Potential Barrier: The accumulated stationary ions create an internal electric field that prevents further carrier diffusion. This potential difference is called the potential barrier (\(0.7\,\text{V}\) for silicon and \(0.3\,\text{V}\) for germanium).

Effects of Biasing

1. Forward Biasing

The positive terminal of an external DC source is connected to the P-side, and the negative terminal to the N-side.
The external electric field opposes the internal potential barrier, repelling majority carriers towards the junction.
This reduces the width of the depletion region and lowers the barrier height. Once the applied voltage exceeds the potential barrier (greater than \(0.7\,\text{V}\) for silicon), a large electric current flows through the junction.

2. Reverse Biasing

The positive terminal is connected to the N-side, and the negative terminal to the P-side.
The applied voltage aids the internal potential barrier, pulling free electrons and holes away from the junction.
This widens the depletion layer and increases the barrier height, preventing majority carrier flow. Only a negligible reverse saturation current flows due to minority charge carriers.

3. Using a diagram, explain how a solid-state relay works and its advantages over mechanical relays.

Working of a Solid-State Relay (SSR)

A Solid-State Relay (SSR) is an electronic switching device that switches load circuits on or off without any moving mechanical parts.

Diagram:

              SOLID-STATE RELAY (SSR)

 Control Input                         Output Load Circuit
  (Low Power)                            (High Power)

 + ────────────┐                       ┌──────────── AC
               ▼                       │
          ┌─────────┐  Optical Light  ┌───────────┐
          │   LED   │ ═════════════►  │ Photo-    │ ───► Load
          └─────────┘  (Isolation)    │ TRIAC/SCR │
 - ────────────┘                      └───────────┘
                                            │
                                      Neutral/GND

Control Side (Input): When a low DC control voltage is applied to the SSR input, an internal Light Emitting Diode (LED) turns on and emits infrared light.
Optical Isolation: The light travels across a transparent insulating barrier to a photosensitive semiconductor device, such as a Photo-TRIAC or phototransistor. This provides electrical isolation between control and load circuits.
Switching Side (Output): The photosensitive element conducts upon receiving light, triggering the main power switching semiconductor (TRIAC/MOSFET) to energise the high-power load circuit.

Advantages of Solid-State Relays over Mechanical Relays

No Moving Parts: Operates silently without mechanical wear and tear, providing an extremely long operational lifespan.
Fast Switching Speed: Switches in microseconds (\(\mu s\)) compared to milliseconds (ms) for electromechanical armatures.
No Contact Arcing/Bouncing: Eliminates electrical arcing, sparks, and contact bounce noise, making it safe for explosive environments.
High Optical Isolation: Prevents high-voltage line surges from damaging sensitive microcontrollers.

4. Describe how an NPN transistor operates, focusing on the movement of charge carriers.

Structure and Biasing of an NPN Transistor

An NPN transistor consists of a thin P-type base layer sandwiched between an N-type emitter and an N-type collector.

For active amplification, it is biased with:

Emitter-Base Junction: Forward biased (low input resistance).
Collector-Base Junction: Reverse biased (high output resistance).

Carrier Movement and Operation

1. Injection from Emitter

The forward bias across the emitter-base junction pushes a vast quantity of majority carrier electrons from the heavily doped N-type emitter into the thin P-type base region.

2. Recombination in Base

The base region is very thin and lightly doped with holes. As electrons enter the base, only a small fraction (less than 2% to 5%) recombines with holes to form the small base current (\(I_B\)).

3. Collection at Collector

The remaining majority (over 95% to 98%) of electrons diffuse through the thin base layer and reach the collector junction. The strong attractive potential of the reverse-biased collector-base junction sweeps these electrons into the collector region, forming the collector current (\(I_C\)).

Current Relation Equation

Applying Kirchhoff’s Current Law to the transistor:

\[ I_E=I_B+I_C \]

5. How can a transistor function as a switch? Provide examples of its use in circuits.

Working Principle of a Transistor as a Switch

A transistor operates as an electronic switch by driving it between its two extreme operational states: Cut-off (OFF state) and Saturation (ON state).

Circuit Diagram:

       + V_CC (Power Supply)
          │
          │
         [ ] Load (e.g., Relay/Lamp)
          │
          ├── Collector (C)
 Input ───┤ Base (B)  NPN Transistor
 V_in     └── Emitter (E)
          │
        GND (0 V)

1. OFF State (Cut-off Region)

When the input base voltage \(V_{\text{in}}\) is zero or below the cut-off threshold (\(V_{BE}<0.7\,\text{V}\)), the base-emitter junction remains unbiased.
No base current flows (\(I_B=0\)), causing \(I_C=0\). The collector-emitter path acts as an open circuit (OFF switch).

2. ON State (Saturation Region)

When a sufficiently high input voltage \(V_{\text{in}}\) is applied (\(V_{BE}\geq0.7\,\text{V}\)), a high base current \(I_B\) drives the transistor into full saturation.
The collector-emitter voltage drops nearly to zero (\(V_{CE(\text{sat})}\approx0.2\,\text{V}\)), allowing maximum collector current \(I_C\) to flow. The path acts as a closed circuit (ON switch).

Circuit Examples

Automatic Street Light Control: A Light Dependent Resistor (LDR) in a voltage divider turns the transistor switch ON at night and OFF during daylight.
Microcontroller Output Driver: Drives heavy inductive loads such as DC motors, solenoids, or buzzers using low-voltage control signals from microcontrollers.

6. Explain the working of an OR gate with a circuit diagram. How does it process input signals?

Definition and Symbol

An OR gate is a basic logic gate that performs logical addition. Its output is high (‘1’) if at least one of its inputs is high (‘1’).

Symbol:

  A ───┐
       ├───)────── X = A + B
  B ───┘

Diode Realisation Circuit Diagram

An OR gate can be realised electronically using two PN junction diodes and a pull-down resistor.

       D1
  A ───►|───┐
             │
       D2    ├────┬──── X (Output)
  B ───►|───┘    │
                 [R] Resistor
                  │
               GND (0 V)

Operation and Signal Processing

Inputs A = 0, B = 0: Both diodes \(D_1\) and \(D_2\) are unbiased/off. No current flows through resistor \(R\), resulting in output \(X=0\,\text{V}\) (Logic ‘0’).
Input A = 1 (5 V), B = 0: Diode \(D_1\) becomes forward biased and conducts current through \(R\), raising output \(X\) to logic ‘1’ (5 V).
Input A = 0, B = 1 (5 V): Diode \(D_2\) becomes forward biased and conducts, raising output \(X\) to logic ‘1’ (5 V).
Inputs A = 1 (5 V), B = 1 (5 V): Both diodes \(D_1\) and \(D_2\) are forward biased and conduct, producing output \(X\) at logic ‘1’ (5 V).

Truth Table

Input A	Input B	Output \(X=A+B\)
0	0	0
1	0	1
0	1	1
1	1	1

7. How are logic gates used in burglar alarms and fire extinguishers? Explain with examples.

1. Burglar Alarm System (Using NAND/OR/AND Gates)

Scenario: A burglar alarm system monitors a door sensor (\(D\)) and a window sensor (\(W\)). The system produces an output alarm signal (\(A\)) whenever either sensor is tripped.
Logic Gate Used: OR Gate (or a combination of logic gates with an active ENABLE switch using an AND Gate).

Diagram:

  Door Sensor (D) ───┐
                     ├───)──── Alarm Output (A)
  Window Sensor (W) ─┘       OR

Working Example:

When both the door and window are closed, \(D=0\) and \(W=0\), so Alarm = 0 (Silent).
If an intruder opens the door (\(D=1\)) OR breaks a window (\(W=1\)), the OR gate output becomes logic ‘1’, activating the security siren.

2. Automatic Fire Extinguishing System (Using AND Gate)

Scenario: To prevent false alarms, a fire suppression system requires inputs from both a temperature sensor (\(T\)) and a smoke detector (\(S\)) before releasing the extinguishing agent.
Logic Gate Used: AND Gate.

Diagram:

  Smoke Sensor (S) ─────┬──────┐
                        │ AND  ├──── Sprinkler/Extinguisher
  Temperature Sensor (T)┴──────┘      Activation

Working Example:

If smoke alone is detected (\(S=1,T=0\)), the output is 0 (No action).
If heat alone rises (\(S=0,T=1\)), the output is 0 (No action).
Only when both high temperature AND smoke are present (\(S=1\) AND \(T=1\)), the AND gate output becomes ‘1’, activating the fire extinguisher system.

8. Discuss the challenges in the development of quantum computers.

Quantum computing uses quantum bits (qubits) operating on principles of superposition and entanglement. Despite immense theoretical speed, several severe physical and engineering challenges hinder practical development.

1. Decoherence and Environmental Interference

Quantum states are extremely fragile. Minor environmental disturbances such as electromagnetic noise, thermal fluctuations, or cosmic radiation cause decoherence, causing qubits to lose their quantum state and corrupting computations.

2. Quantum Error Correction

Unlike classical bits, qubits cannot be directly copied due to the No-Cloning Theorem. Implementing quantum error correction requires thousands of physical qubits to protect a single logical qubit, vastly increasing hardware complexity.

3. Extreme Operating Conditions (Cryogenics)

Most leading quantum systems, such as superconducting qubits, require near absolute zero temperatures (around \(15\,\text{mK}\) or \(-273.13^\circ\text{C}\)) maintained by dilution refrigerators, making operation energy-intensive and costly.

4. Scalability and Hardware Fabrication

Fabricating millions of identical, high-fidelity physical qubits on an integrated chip while controlling interconnects and readout lines without thermal leakage remains an immense manufacturing bottleneck.

Numerical Response Questions

Q1. In a junction transistor, emitter current is \(5.82\,\text{mA}\) and base current is \(120\,\mu\text{A}\). Calculate the collector current.

Given Data:

– Emitter current:

\[ I_E=5.82\,\text{mA}=5.82\times10^{-3}\,\text{A} \]

– Base current:

\[ I_B=120\,\mu\text{A} \]

\[ I_B=120\times10^{-6}\,\text{A} =0.12\,\text{mA} \]

To Find:

Collector current (\(I_C=?\))

Formula:

\[ I_E=I_B+I_C \]

Rearranging:

\[ I_C=I_E-I_B \]

Step-by-Step Solution:

Substitute the values into the formula:

\[ I_C=5.82\,\text{mA}-0.12\,\text{mA} \]

\[ I_C=5.70\,\text{mA} \]

Answer: The collector current is \(5.7\,\text{mA}\).

Q2. For a \(600\,\mu\text{A}\) base current and \(30\,\text{mA}\) collector current, how much is the current gain \(\beta\)?

Given Data:

– Base current:

\[ I_B=600\,\mu\text{A} =600\times10^{-6}\,\text{A} =0.6\,\text{mA} \]

– Collector current:

\[ I_C=30\,\text{mA} =30\times10^{-3}\,\text{A} \]

To Find:

Current gain (\(\beta=?\))

Formula:

\[ \beta=\frac{I_C}{I_B} \]

Step-by-Step Solution:

Substitute the given values into the formula:

\[ \beta=\frac{30\,\text{mA}}{0.6\,\text{mA}} \]

\[ \beta=\frac{30}{0.6}=50 \]

Answer: The current gain \(\beta\) is 50.

Q3. Calculate the value of \(\beta\) gain if an emitter current is changed by \(4\,\text{mA}\) and the collector current is changed by \(3.5\,\text{mA}\).

Given Data:

– Change in emitter current:

\[ \Delta I_E=4\,\text{mA} \]

– Change in collector current:

\[ \Delta I_C=3.5\,\text{mA} \]

To Find:

Current gain (\(\beta=?\))

Formulas:

1. From the transistor current relation:

\[ \Delta I_E=\Delta I_B+\Delta I_C \]

Therefore:

\[ \Delta I_B=\Delta I_E-\Delta I_C \]

2. Current gain:

\[ \beta=\frac{\Delta I_C}{\Delta I_B} \]

Step-by-Step Solution:

Step 1: Calculate the change in base current (\(\Delta I_B\)).

\[ \Delta I_B=4\,\text{mA}-3.5\,\text{mA} \]

\[ \Delta I_B=0.5\,\text{mA} \]

Step 2: Calculate the current gain (\(\beta\)).

\[ \beta=\frac{3.5\,\text{mA}}{0.5\,\text{mA}} \]

\[ \beta=\frac{3.5}{0.5}=7 \]

Answer: The current gain \(\beta\) is 7.

Notes by Sir Dilawar
For more notes, visit QuranEducationPoint.com